WAN and VLAN Solutions
Division of labour principle
- Control plane functions include the system configuration, system management, maintenance of forwarding tables and maintenance of network topology information.
- Less strict performance requirements
- Not applied to every input frame
- Datapath functions include forwarding decisions, data transfer and data scheduling.
- Very strict performance requirements
- Applied to every input frame
Development of datapath architectural patterns
Shared bus, multiple CPUs
Architectural importance of fixed-size frames
- Packets are variable-size frames, most often associated with IP data
- Cells are fixed-size frames, most often associated with ATM data
Classification of switching fabrics
architectures multiplex input frames and forward them through a single data path
connecting all input and output ports.
- Simpler architecture whose performance is primarily dependent on capacity of the internally shared medium (memory or bus)
- Capacity of the shared medium is typically required to be at least equal to the number of ports multiplied by the capacity per port
- Easier to support broadcast/multicast operations because the data path is connected to all ports
- Cost effective implementation for switches with small number of ports (64 or less)
architectures have multiple data paths
available between the input and output ports, in which a subset of the paths can transmit data simultaneously
- Total switching capacity is calculated by multiplying the capacity of each data path by the number of paths that can transmit simultaneously
- Single path architectures have only one path for any input-output pair, which results in simpler path control
- Multipath architectures have more than one path for any input-output pair, which improves connection flexibility and redundancy
Shared bus architecture
Shared memory architecture
Basic crossbar architecture
- Nonblocking property means that a connection is always possible between any idle input port and any idle output port
- Each output port may connect to zero or one input port
- The output vector describes the simultaneous active (parallel) connections
- The Φ symbol in the output vector indicates that the output port is not connected to an input port. Using that notation:
- the output vector for a switch without traffic is [ Φ, Φ, Φ, Φ ]
- the output vector for 1 multicast and 2 unicast connections is [ 2, 4, 2, 1 ]
- the output vector for a broadcast connection is [ 2, 2, 2, 2 ]
- Input and output of corresponding port numbers are physically the same port
Asymmetric crossbar architectures
Banyan-based switch architectures
- An N x N switch fabric requires k stages using identical b x b switching nodes, where N = bk
- There is exactly one connection path from any input to any output
- Self-routing property means that the connection path is described with a unique n-bit destination address, where each bit indicates an output port at each stage
Four types of banyan-based architectures
- shuffle exchange
- reverse shuffle exchange
Internal blocking may occur with banyan architectures
Batcher-banyan architecture to avoid internal blocking
A banyan switch can avoid internal blocking by using a pre-processing sorting network to
- Concentrate input ports so that there are no idle ports between any two active input ports
- Sort destination addresses in either ascending or descending order
Clos multipath architecture
Stages of the Clos architecture have specific roles:
- Each stage 1 crossbar accepts input from n sources and redistributes the traffic to m outputs, which are connected to stage 2 crossbars.
- Each stage 3 crossbar accepts connections from m stage 2 crossbars and delivers the rearranged traffic to the n connected output ports.
- Each stage 2 crossbar has a link from each stage 1 crossbar and to each stage 3 crossbar.
The integers n
, and r
determine the overall size of the Clos network.
- There are r stage 1 crossbars. As each accepts n links, stage 1 as a whole accepts N = rn input links.
- There are r stage 3 crossbars. As each has n output links, stage 3 as a whole has N = rn output links.
- Each of the r stage 1 devices have m output links, so stage 1 as a whole has rm output links to stage 2.
- Each of the r stage 3 devices accepts m input links, so rm output links connect stage 2 to stage 3.
- Each stage 2 device is connected to each stage 1 device with one link.
- Each stage 2 device is connected to each stage 3 device with one link.
Commercial products and research papers